The 256th Apple is also a RISC-V programmer, and what kind of processor is RISC-V?: Brain talk

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　I have already written about "RISC-V" several times.The news that Apple recruits RISC-V engineers has been flowing recently (Apple's job information "RISC-V High Performance Programmer" [English]).This time, without business political stories, I would like to think of which side of RISC-V is purely wonderful (or how it changes compared to ARM or X86).

　First of all, I would like you to keep in mind that RISC-V is a standard for classical computer architecture "ISA (instruction set architecture)".Modernly, it is sometimes referred to as "(micro) architecture", including the structure inside the processor, but in the classic definition, there is no implementation of what circuit to be implemented (implementation).

　A long time ago, the textbook of VAX (Digital Equipment Corporation), which was a mini -controller star, stated that "architecture is a keyboard" and "the structure of an implementation is an imaging piano or an upright piano."I have a memory.Here is a pianist but a system -level programmer.

　ABI (Application Binary Interface: Application Binary Interface (Application Binary Interface: Application Binary Interface), which is a view of the assembler visible from the programmer, encoding it to the machine language, description of changes in registers and memory when operating the order, privileged mode and virtual memory, and how to use registers and stacks.The RISC-V is determined by the binary-level interface between the program and the OS / library.

　All are described as documents, and the summary is summarized in two sides of the two -sided reference card.If you point out a word here, you can make simple things cheaply.

　Well, such an architecture exists in ARM or X86.However, RISC-V is different from these existing processors and their ideas."Modular" vs "incremental".

　I don't know if it's an analogy of young people, but existing processors have expanded in an increase in hot spring inns.We will build a main building, create an annex, and build a new building one after another.Old buildings also renovate and expand.Then, connect the corridor between them.A huge but complex maze is completed.Occasionally, old buildings are demolished and landed.Since it is planned according to the demand on the spot, it is locally reasonable, but the consistency throughout is low.

　On the other hand, RISC-V is a modular.The foundation is "RV32I", a "frozen" instruction set (can be relied on that programmers can always be used).This part is common from built-in RISC-V microcomputers to HPCs (although it is adopted).

　On top of that, various extensions such as multiplication, floating point, atomic, vector, and privileges are defined.If you actually implement a chip, the style is used by combining them as appropriate.You can make a minimal one cheaply, or to make a maximum one.And all expansions are planned to have no contradiction.

　Here is an example of extension.16 -bit length instructions are effective in reducing program code.It is a function you want in a limited memory.ARM was originally a 32 -bit fixed length, but added a 16 -bit length instruction set called "Thumb" for embedding.In the incorporation of the Cortex-M series, etc., a 32-bit / 16-bit instruction set called "Thumb-2" (the name is confusing but not upward compatible with Thumb).And even if there is a processor that implements all of those instructions, they cannot mix those instructions in one context.You need to switch.

　On the other hand, let's look at RISC-V.The basic RISC-V can use 32-bit registers with 32-bit fixed length orders.The 16 -bit length instruction (16 32 -bit registers can be used) is also defined as an extension.

　However, the encoding of the machine language order has been assigned to be OK even if 16 bits and 32 bits are mixed.And all 16 -bit length instructions can be specified by the 32 -bit length order.The 16 -bit length instruction can only be operated with 16 registers, but it is a completely subset.

　And the 16 -bit long order is assigned to a register for registers that are expected to be used frequently in the 32 -bit long order.ABI is also compatible.In other words, if you re -assemble a program source that can be operated on a 32 -bit fixed length processor that does not have a 16 -bit length, for a target with a 16 -bit long -compatible "extension", the object code size is the object code size.Decrease.The effect should be great because "shortening" is defined, focusing on high -frequency instructions.

　For this kind of consideration, the encoding of the RISC-V machine language instructions and the assignment of the ABI register seem to be a strange way to allocate the existing processor.

　However, the strange allocation has been considered to be able to expand without contradiction, and then consider that the hardware will be small at the time of implementation.The RISC-V does not tie hardware implementation, but is determined after being examined deeply so that it can be implemented with small and fast hardware.

　The RISC-V, 20 years after ARM, is also learning past processors failure.The definitions that were hand -taught at the time of introduction, but have become a problem later have been eliminated.For example, "delay branch instructions", "conditional execution", and "stack frame generation orders" do not exist in RISC-V.

　So, if you look at the instruction set, it looks like there is no minimum and no characteristics.However, if you look closely, you will be able to take into account the details and increase the efficiency with a simple instruction.

　RISC-V, under the remorse of the expansion of a hitting expansion, such as putting a house on a past processor, pulls the implementation feet so that there is no contradiction in consideration of expandability from the beginning.You've understood that you don't have such strange features.

　So, RISC-V International (organizations that set this architecture standard) are still working on expansion, but I don't think they will give out easy expansion.It seems that one company does not decide on its own, decides in the open discussion of each member's organization, and always examines whether it is in line with the basic concept.

　In such an extension, the vector extension is considered to be attracting attention in the development of high -end models in the future.RISC-V's "V" is a part that is also said to be "V" of "vector".This is an antithesis for the SIMD instruction of ARM and X86.

　Have you ever written a SIMD instruction in Assembler?The SIMD instruction itself can handle many elements at once, but it is very difficult to prepare and prepare to bring it to SIMD.If you are thinking about processing such as the part that protrudes from the width of the SIMD instruction, you will feel crazy.I want you to stop sparse queues (altered queues: Most of the ingredients are "0") (there are many real problems).

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